2019 Program

The 15th IEEE Workshop on Silicon Errors in Logic – System Effects (SELSE 2019)
27–28 March 2019, Stanford University, Palo Alto, California

Program 2019

Day 1 – March 27, 2019
08:00 – 08:45 Breakfast and Registration
08:45 – 09:00 Welcome Remarks: SELSE General and Program Chairs
09:00 – 10:00 Session I: Keynote Talk I (Chair: Laura Monroe) – Title: Complications in the Integration of Commercial Microprocessors in Harsh Radiation Environments
         Speaker: Heather Quinn, LANL
10:00 – 10:30 Coffee Break
10:30 – 12:00 Session II: Evaluation Techniques for Resilient Systems (Chair: Michael Sullivan)

  • Generation of stressmarks for early stage soft-error modeling
    • Karthik Swaminathan, Ramon Bertran, Hans Jacobson, Prabhakar Kudva and Pradip Bose
  • A High-Fidelity, Low-Overhead and Open-Source Timing Error Injector
    • Chun-Kai Chang and Mattan Erez
  • Equivalence of neutron and proton in SEE testing
    • Yueh Chiang, Cher Tan, Tsi-Chian Chao, Chung-Chi Lee and Cj Tung

12:00 – 13:00 Lunch
13:00 – 14:00 Session III: Panel Discussion (Chairs: John Daly and Laura Monroe)
         Title: New Technology and Reliability.
         Speakers: Dave Mountain (LPS), Rich Murphy (Micron), Dilip Vasudevan (LBL)
14:00 – 15:30 Session IV: Resilience Characterization of GPU-based Accelerators  (Chair: Mark Gottscho)

  • Towards analytically evaluating the error resilience of GPU Programs
    • Abdul Rehman Anwer, Guanpeng Li, Karthik Pattabiraman, Siva Kumar Sastry Hari, Michael Sullivan and Timothy Tsai
  • On the Trend of Resilience for GPU-Dense Systems
    • Kyushick Lee, Michael Sullivan, Siva Hari, Timothy Tsai, Stephen Keckler and Mattan Erez
  • An extended GPGPU model to support detailed reliability analysis
    • Josie Esteban Rodriguez Condia and Matteo Sonza Reorda

15:30 – 16:00 Coffee Break
16:00 – 16:45 Session V: Special Session I (Chair: Karthik Swaminathan)

            Title: A platform for evaluating resilience for end-to-end learning in autonomous systems

            Speaker: Vijay Janappa Reddi, Harvard

16:45 – 17:30 SELSE Business Meeting
17:30         Reception
 
Day 2 – March 28, 2019
08:00 – 09:00 Breakfast
09:00 – 10:00 Session VI:  Keynote Talk II (Chair: John Daly) – On Exploiting the Synergy Between Reliability and Security
         Speaker: Moin Qureshi, Georgia Tech
10:00 – 10:30 Coffee Break
10:30 – 12:00 Session VII: Special Session (Chairs: Karthik Swaminathan and Siva Hari)

  • An overview of DNN systems and Resilience Challenges
    • Siva Hari (NVIDIA)
  • Resilience-aware circuits and architectures for DNNs
    • Karthik Swaminathan (IBM)
  • Mixed-Signal Circuits for Inference at the Edge
    • Danny Bankman (Stanford)

12:00 – 13:15 Lunch
13:15 – 14:15 Session VIII: Machine Learning and Resilience (Chair: Vanessa Job)

  • Efficient Inference at the Edge with Fault Resilient Voltage Scaling of Embedded Memories
    • Irina Alam and Puneet Gupta
  • Machine Learning To Tackle the Challenges of Transient and Soft Errors in Complex Circuits
    • Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu and Luca Sterpone

14:15 – 14:30 Break
14:30 – 15:30 Poster Session (Chair: Alan Wood) and Coffee Break

  • 16nm Floating Gate NAND Flash Soft Error Susceptibility
    • Sandhya Chandrashekhar, Helmut Puchner, Jun Mitani, Satoshi Shinozaki, Mohamed Sardi and David Hoffman
  • An optically reconfigurable gate array workable under a strong gamma radiation environment
    • Takumi Fujimori and Minoru Watanabe
  • Equivalence of neutron and proton in SEE testing
    • Yueh Chiang, Cher Tan, Tsi-Chian Chao, Chung-Chi Lee and Cj Tung
  • An extended GPGPU model to support detailed reliability analysis
    • Josie Esteban Rodriguez Condia and Matteo Sonza Reorda

15:30 – 16:45 Session IX: Panel Discussion (Chair: Siva Hari)
         Title: Autonomous Systems’ Safety and Reliability
         Speakers: Richard Bramley (NVIDIA), Jyotika A. Athavale (Intel), Dave Kelf (Optima Design Automation), Pierre Maillard (Xilinx)
16:45 – 17:00 Closing Remarks