Program

The 16th IEEE Workshop on Silicon Errors in Logic – System Effects (SELSE 2020)

February 19 – February 20, 2020, Stanford University, CA, USA

Program 2020

Day 1 – February 19, 2020

08:00 – 08:45 Breakfast and Registration

08:45 – 09:00 Welcome Remarks: SELSE General and Program Chairs

09:00 – 10:00 Session I: Keynote Talk I (Chair: John Daly)

  • The Robust Computing Systems: From Today to the NanoSystems Era

                Subhasish Mitra (Stanford U.)

10:00 – 10:30 Coffee Break

10:30 – 12:00 Session II: Machine Learning and Reliability (Chair: Vanessa Job)

  • An Input-aware Learning-based Error Model of Voltage-Scaled Functional Units

                Dongning Ma and Xun Jiao

  • Multivariant Outlier Analysis for No Trouble Found (NTF) Customer Returns

                Komal Soni, Thong Tran, Sudheer Reddy Gundala, Adam Fogle, Sandhya Chandrashekhar and Aaron Baker

  • Machine Learning Clustering Techniques for Selective Mitigation of Critical Design Features

               Thomas Lange, Dan Alexandrescu, Maximilien Glorieux, Aneesh Balakrishnan and Luca Sterpone

 

12:00 – 13:00 Lunch

13:00-13:30 Session III: Mariia Mykhailova (Microsoft)   (Chair, Xiang Guan)

13:30-13:45 Thien Nguyen (ORNL)

  • Quantum Error Correction Tutorial with Q#

13:45-14:00 Lei Xie (Tsinghua University)

  • Fault-Tolerant Quantum Error Correction using the Steane Error Correction Scheme

14:00 – 15:00 Session IV: Fault tolerance and GPUs  (Chair: Stefano Di Carlo)

  • Software-only Triple Diverse Redundancy on GPUs for Autonomous Driving Platforms

Sergi Alcaide Portet, Leonidas Kosmidis, Carles Hernandez and Jaume Abella

  • Green-ABFT: Energy Efficient and Fault Tolerant Cholesky Decomposition on Heterogeneous Systems with GPUs

                Jieyang Chen, Xin Liang, Sihuan Li, Kaiming Ouyang, Kai Zhao, Qiang Guan, Dan Wang and Zizhong Chen

15:00 – 15:30 Coffee Break

15:30 – 16:30 Session V: Special Session — Neutron experiments in ARM® architectures (Chair: TBD)

  • A Comparison of Soft Errors in 28nm Planar and 16nm FinFET ARM® Cortex®-A72 cores while exposed to Accelerated Neutron Testing

            Charles Corley, Gary Anderson, Giovanny Vasquez and Earl Swartzlander

  • Inducing Silent Data Corruption in ARM® Cortex®-A72 cores while exposed to Accelerated Neutron Testing

            Charles Corley, Gary Anderson, Giovanny Vasquez and Earl Swartzlander.

 

16:30 – 17:00 SELSE Business Meeting

Day 2 – February 20, 2020

08:00 – 09:00 Breakfast

09:00 – 10:00 Session VI:  Keynote Talk II (Chair: Stefano Di Carlo)

         Speaker: Matthew Marinella (Sandia)

  • Efficient Neural Network Processing Using Analog In-Memory Computing

10:00 – 10:30 Coffee Break

10:30 – 11:30 Session VII: Reliability and Functional Safety (Chair: Qiang Guan)

  • Reliability evaluation of neural networks in GPGPUs: SEU effects in the scheduler controller

                Josie Esteban Rodriguez Condia, Matteo Sonza Reorda, Paolo Rech and Fernando Fernandes dos Santos

  • Hierarchical Reliability and Functional Safety Evaluation Through Machine-Learning

                Dan Alexandrescu, Aneesh Balakrishnan, Thomas Lange and Maximilien Glorieux

11:30 – 12:30 Session VIII: Radiations (Chair: Sandhya Chandrashekhar)

  • Radiation-hardened optically reconfigurable gate array using a multi-wavelength holographic memory

                Junya Ishido and Minoru Watanabea

  • Thermal Neutrons: a Possible Threat for Supercomputers and Safety Critical Applications

                Daniel Oliveira, Sean Blanchard, Nathan DeBardeleben, Fernando Santos, Gabriel Piscoya Davila, Philippe Navaux, Stephen Wender, Carlo Cazzaniga, Christopher Frost, Robert Baumann and Paolo Rech

12:30 – 12:45 Closing Remarks (Stefano Di Carlo)

12:45 – 13:45 Lunch