2011 Call for Participation
Workshop on Silicon Errors in Logic – System Effects (SELSE 2011)
University of Illinois— March 29-30, 2011
- Key areas of interest are (but not limited to):
- Technology trends and the impact on error rates.
- New error mitigation techniques.
- Characterizing the overhead and design complexity of error mitigation techniques.
- Case studies describing the engineering tradeoffs necessary to decide what mitigation
- technique to apply.
- Experimental data.
- System-level models: derating factors and validation of error models.
- Error handling protocols (higher-level protocols for robust system design).
Authors may submit extended abstracts for paper presentation, poster presentation, or either format. The extended abstracts for accepted posters are included in the workshop proceedings. Authors are requested to submit their extended abstracts for review before December 23, 2010. Additional information and guidelines for submission are available at www.selse.org. Submissions should be PDF or Microsoft Word files that do not exceed four printed pages. Customary terms for copyright agreement and non-confidentiality will apply. Authors will be notified of paper outcome by February 17, 2011. Camera-ready formatted papers, up to six pages in length, are due on March 17, 2011.
Organizing committee (see www.selse.org/committee for complete membership):
Local Arrangements Chair: Publicity Chair:
Vikas Chandra, ARM Vilas Sridharan, AMD Rakesh Kumar, UIUC Vivian Zhu, TI