2011 Program

SELSE 7 Program

 SELSE is an informal workshop. To encourage widespread participation authors are given the option to not have their papers or presentations published on this web site. We thank all authors for their participation.
Workshop Venue: Room B02, Coordinated Science Laboratory, 1308 W. Main Street, Urbana, IL
Day 1 – March 29th, 2011 – University of Illinois, Champaign-Urbana
08:30 – 09:15 Breakfast and Registration
09:15 – 09:30 Welcome
09:30 – 10:30 Session I (Session Chair: Sarah Michalak)
DOE’s Exascale Initiative and Resilience
Josip Loncaric.
10:30 – 10:45 Break
10:45 – 12:15 Session II: Beam Testing (Session Chair: Alan Wood)
Neutron Beam Testing Triblades.
Sarah Michalak, Andrew DuBois, Curtis Storlie, William Rust, David DuBois, David Modl, Heather Quinn, Andrea Manuzzato and Sean Blanchard.
Thermal Neutron SER Testing and Analysis: Findings from a 32nm HKMG SRAM case study.
Ming Zhang, Jongwoo Park, Gunrae Kim, Kee Sup Kim, Remi Gaillard and Olivier Lauzeral.
Quantification & Mitigation Techniques of Soft-Error Rates in Routers Validated in Accelerated Neutron Irradiation Test and Field Test.
Ken-ichi Shimbo, Tadanobu Toba, Koji Nishii, Eishi Ibe, Fellow, IEEE, Yoshio Taniguchi and Yasuo Yahagi.
12:15 – 13:15 Launch
13:15 – 14:45 Session III: Software Testing (Session Chair: Vilas Sridharan)
Relyzer: Application Resiliency Ananlyzer for Transient Faults.
Siva Kumar Sastry Hari, Helia Naeimi, Pradeep Ramachandran and Sarita V. Adve.
Improving Microprocessor Reliability Through Software Mitigation.
Heather Quinn, Justin Tripp, Tom Fairbanks and Andrea Manuzzato.
A Case for Timing Error Resilience-Aware Compilation.
John Sartori and Rakesh Kumar.
14:45 – 15:00 Break
15:00 – 16:30 Session IV: Modeling & Analysis (Session Chair: William Robinson)
An SER Analysis Method for Sequential Circuits.
Masayoshi Yoshimura, Yusuke Akamine and Yusuke Matsunaga.
Analytic Error Modeling for Imprecise Arithmetic Circuits.
Jiawei Huang, John Lach and Gabriel Robins.
Single Event Study of an DC-DC Converter.
Yi Ren, Li Chen, Shi-Jie Wen, Rick Wong, Chiate Lin and Bharat Bhuva.
16:30 – 16:45 Break
16:45 – 17:45 CCC Update
Study on Cross-Layer Reliability.
Heather Quinn.
18:00 Reception
Day 2 – March 30th, 2011 – University of Illinois, Champaign-Urbana
08:00 – 08:30 Breakfast and Registration
08:30 – 10:00 Session V: Microarchitecture/System-level Detectors (Session Chair: Babak Falsafi)
CBFD: A Count-Based Fault Detection Scheme for Memory Arrays.
Yiannakis Sazeides, Bushra Ahsan, Isidoros Sideris, Lorena Ndreu, Sachin Idgunji and Emre Ozer.
Understanding When Symptom Detectors Work by Studying Data-Only Application Values.
Pradeep Ramachandran, Siva Kumar Sastry Hari, Sarita Adve and Helia Naeimi.
CrashTest’ing SWAT: Accurate, Gate-Level Evaluation of Symptom-Based Resiliency Solutions.
Andrea Pellegrini, Rob Smolinski, Lei Chen, Xin Fu, Siva Kumar Sastry Hari, Junhao Jiang, Sarita Adve, Todd Austin and Valeria Bertacco.
10:00 – 10:15 Break
10:15 – 11:45 Session VI: Measurement & Statistics (Session Chair: Helia Naeimi)
MTTF Measurement Under Alpha Particle Radiation in a Coarse-Grained Reconfigurable Architecture with Flexible Reliability.
Dawood Alnajjar, Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto and Takao Onoye.
Engineering of Error Statistics for Energy-Efficient Robust Digital Signal Processing Systems.
Rami Abdallah, Yu-Hung Lee and Naresh Shanbhag.
Revisions to the JEDEC JESD89 Standard on Soft Error Measurement.
Charles Slayman.
11:45 – 12:45 Launch
12:45 – 14:00 Poster Session
Synthesis optimization trends on error propagation probability of combinational circuits.
Daniel Limbrick, William Robinson and Bharat Bhuva.
FPGA CRAM Soft Error Analysis Approach for Reliable Networking System.
Haihong Zhu, Shijie Wen, Rick Wong, Gary Swift and Ali Nouri.
A Robust Algorithm for Pessimistic Analysis of Logic Masking Effects in Combinational Circuits.
Taiga Takata and Yusuke Matsunaga.
An End-to-End ECC-based Resiliency Approach for Microprocessors.
Helia Naeimi.
LABIR: Inter-LAyer Built-In Reliability for Electronic Components and Systems.
Eishi Ibe, Ken-ichi Shimbo, Tadanobu Toba, Hitoshi Taniguchi and Yoshio Taniguchi.
14:00 – 15:30 Session VII: Soft Error (Session Chair: Rakesh Kumar)
An Improved Approach to Characterizing Alpha-Induced Upset Susceptibility.
Gary Swift.
Multiple-Bit-Upset Tolerant 8T SRAM Cell Layout with Divided Wordline Structure.
Shusuke Yoshimoto, Takuro Amashita, Daisuke Kozuwa, Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Hiroshi Kawaguchi and Masahiko Yoshimoto.
The Impact of New Technology on Soft Error Rates.
Alan Wood and Anand Dixit.
15:30 – 15:45 Break
15:45 – 16:45 Discussion on Datacenters/Harsh environments
16:45 – 17:00 Closing Remarks