2016 Program

SELSE-12 Program

The SELSE Program Committee is proud to announce our keynote speakers for SELSE-12!
Keynotes:
Keynote I: Can the end of Moore’s law result in new opportunities for computing?
Dr. Krishna V. Palem (Rice University)
Keynote II: Autonomous Car is the New Driver for Resilient Computing and Design-for-Test
 Dr. Nirmal R. Saxena (NVIDIA)
Keynote III: Quantum error correction and quantum algorithmic discovery
 Dr. Martin Roetteler (Microsoft Research)
Day 1 – March 29, 2016 – Austin, TX
08:00 – 08:45 Breakfast and Registration
08:45 – 09:00 Welcome Remarks: SELSE General and Program Chairs
09:00 – 10:00 Session I: Keynote Speech (Chair: TBD)
Can the end of Moore’s law result in new opportunities for computing?
Dr. Krishna V. Palem (Rice University)
10:00 – 10:30 Coffee Break
10:30 – 11:45 Session II: Memory Resilience (Chair: TBD)
Software-Defined Error-Correcting Codes
Mark Gottscho (UCLA), Clayton Schoeny (UCLA), Lara Dolecek (UCLA), and Puneet Gupta (UCLA)
A Unified Framework for Error Correction Techniques in On-Chip Memories
Fred Sala (UCLA), Henry Duwe (UIUC), Lara Dolecek (UCLA), and Rakesh Kumar (UIUC)
Improving the Reliability of SRAM FPGA Circuits using Feedback TMR and Configuration Scrubbing
Andrew Keller (BYU), Parker Ridd (Brigham Young U.), Chase McCloskey (Brigham Young U.), Michael Wirthlin (Brigham Young U.), and Heather Quinn (LANL)
11:45 – 13:00 Lunch
13:00 – 14:15 Session III: Panel Discussion (Chair: Laura Monroe (LANL))
Topic: Resilience and Probabilistic Computing
Panelists: Karthik Pattabiraman (UBC), John Daly (DOD), Rakesh Kumar (UIUC), Vilas Sridharan (AMD), Sudhanva Gurumurthi (IBM/U. Virginia)
14:15 – 15:45 Session IV: Poster Session and Coffee Break
MoRV: Modelling Reliability under Variability
Malte Metzdorf (OFFIS), Reef Eilers (OFFIS), Domenik Helms (OFFIS), Kay-Uwe Giering (Fraunhofer EAS), Roland Jancke (Fraunhofer EAS), Gerhard Rzepa (TU Vienna), Tibor Grasser (TU Vienna), Markus Karner (GTS), Praveen Raghavan (IMEC), Ben Kaczer (IMEC), Dan Alexandrescu (iROC tech), Adrian Evans (iROC tech), Gunnar Rott (Infineon), Peter Rotter (Infineon), Hans Reisinger (Infineon), Wolfgang Gustin (Infineon), and Wolfgang Nebel (Carl von Ossietzky Universität Oldenburg)
Evaluating the Resilience of Highly Parallel Applications
Mark Wilkening (Northeastern), Fritz Previlon (Northeastern), Vilas Sridharan (AMD), and David Kaeli (Northeastern)
SpinDIMM: A Reliable Memory Design with Tailored STT-MRAM and Reinforcement Learning
Mustafa Shihab (UT Dallas), Myoungsoo Jung (Yonsei U.), and Joseph Callenes-Sloan (UT Dallas)
On the Inherent Resilience of Integer Operators
Laura Monroe (LANL), William Jones (Coastal U.), Claude Davis (Clemson U.), Scott Lavigne (Coastal U.), Qiang Guan (LANL), and Nathan Debardeleben (LANL)
Correlations between Radiation Hardness and Variation of FFs Depending on Layout Structures in a 28 nm Thin BOX FD-SOI Process by Alpha Particle Irradiation
Haruki Maruoka (Kyoto Institute of Technology U.), Shohei Kanda (Kyoto Institute of Technology U.), Jun Furuta (Kyoto Institute of Technology U.), Kazutoshi Kobayashi (Kyoto Institute of Technology U.), and Masashi Hifumi (Kyoto Institute of Technology U.)
15:45 – 17:00 Session V: Radiation Testing of Devices and Systems (Chair: TBD)
Effects of Passivation and BEOL Layers on Alpha Particle-Induced Soft Error Rate for FinFET SRAM Devices
Soonyoung Lee (Samsung), Taiki Uemura (Samsung), Sangwoo Pae (Samsung), In Hak Baick (Samsung), and Jungman Lim (Samsung)
Reliability Analysis of Modern HPC Parallel Accelerators
Daniel Alfonso Gonçalves De Oliveira (UFRGS), Laércio Pilla (UFSC), Fernando Santos (UFRGS), Caio Lunardi (UFRGS), Philippe Navaux (UFRGS), Luigi Carro (UFRGS), and Paolo Rech (UFRGS)
Evaluating the Radiation Reliability of Dependability-Oriented Real-Time Operating Systems
Thiago Santini (U. Tübingen), Christoph Borchert (TU Dortmund), Christian Dietrich (Friedrich-Alexander-Universität Erlangen-Nürnberg), Horst Schirmeier (TU Dortmund), Martin Hoffmann (Friedrich-Alexander-Universität Erlangen-Nürnberg), Olaf Spinczyk (TU Dortmund), Daniel Lohmann (Friedrich-Alexander-Universität Erlangen-Nürnberg), Flávio Rech Wagner (UFRGS), and Paolo Rech (UFRGS)
17:00 – 17:30 SELSE Business Meeting
18:00              Reception and Banquet
Day 2 – March 30, 2016 – Austin, TX
08:00 – 08:30 Breakfast
08:30 – 09:30 Session VI: Keynote Speech (Chair: TBD)
Autonomous Car is the New Driver for Resilient Computing and Design-for-Test
Dr. Nirmal R. Saxena (NVIDIA)
09:30 – 10:00 Coffee Break
10:00 – 11:40 Session VII: Reliability Modeling and Evaluation (Chair: TBD)
An Analytical Model for Hardened Latch Selection and Exploration
Michael Sullivan (NVIDIA), Brian Zimmer (NVIDIA), Siva Hari (NVIDIA), Timothy Tsai (NVIDIA), and Stephen Keckler (NVIDIA)
System-Wide Reliability Analysis on Real Processor and Application under Vdd and T Stress
Simone Corbetta (IMEC VZW), Wim Meeus (IMEC VZW), Dimitrios Rodopoulos (Natl’ Technical U. of Athens), Etienne Cappe (Thales Communication & Security), Francky Catthoor (IMEC VZW), and Agnes Fritsch (Thales Communication & Security)
Performance Evaluation of compiler-based Redundant Multithreading in an HSA environment
Charu Kalra (Northeastern), Daniel Lowell (AMD), John Kalamatianos (AMD), Vilas Sridharan (AMD), and David Kaeli (Northeastern)
P-FSEFI: A Parallel Soft Error Fault Injection Framework for Parallel Applications
Qiang Guan (LANL), Nathan Debardeleben (LANL), Sean Blanchard (LANL), Panruo Wu (UC Riverside), Laura Monroe (LANL), and Zizhong Chen (UC Riverside)
11:40 – 13:00 Lunch
13:00 – 14:00 Session VIII: Keynote Speech (Chair: TBD)
Quantum error correction and quantum algorithmic discovery
Dr. Martin Roetteler (Microsoft Research)
14:00 – 15:15 Session IX: Resilience Enhancement (Chair: TBD)
CLEAR: Cross-Layer Exploration for Architecting Resilience – Combining Hardware and Software Techniques to Tolerate Soft Errors in Processor Cores
Eric Cheng (Stanford), Shahrzad Mirkhani (Stanford), Lukasz Szafaryn (U. Virginia), Chen-Yong Cher (IBM Research), Hyungmin Cho (Stanford), Kevin Skadron (U. Virginia), Mircea Stan (U. Virginia), Klas Lilja (Robust Chip), Jacob Abraham (UT Austin), Pradip Bose (IBM Research), and Subhasish Mitra (Stanford)
Reduced Precision Checking to Detect Errors in Floating Point Arithmetic
Yaqi Zhang (Stanford), Ralph Nathan (Google), and Daniel Sorin (Duke)
Radiation Hardening Improvement of a SerDes under Heavy Ions up to 60MeV.cm2/mg by Layout-Aware Fault Injection
Benjamin Coeffic (STMicroelectronics), Jean-Marc Daveau (STMicroelectronics), Gilles Gasiot (STMicroelectronics), S. Parini (STMicroelectronics), Thierry Scholastique (STMicroelectronics), Lirida Naviner (Telecom ParisTech), Philippe Roche (STMicroelectronics), and A.E. Pricco (STMicroelectronics)
15:15 – 15:40 Coffee Break
15:40 – 16:10
Session X: Paths Forward for Probabilistic Computing —  
An Update from  IEEE RCS4, Laura Monroe, LANL
16:10 – 17:00 Session XI: Random Access  and Closing Remarks (Chair: TBA)
 

Can the end of Moore’s law result in new opportunities for computing?

Abstract:
Many claim that the laws of physics dictating exponential growth in transistor scaling or Moore’s Law will end in the next 10 to 20 years. This argument is based, in part, on an analysis that switching devices cannot function deterministically as feature sizes get reduced to the molecular level. Moore’s Law, however, could continue if systems with nondeterministic switches could process information usefully. Our group’s research that aims to exploit this principle, dubbed inexact computing, suggests that circuits and computing architectures can be used effectively at nanometer scale. Succinctly put, inexact computing systems allow compromises in accuracy to be traded for significant, often disproportionately high gains in performance and energy consumption. Surprisingly, applications domains ranging from the internet of things with cognitive nodes, to climate modeling and weather prediction, provide great opportunities in this regard. I will review the history of inexact computing, its relationship to computing traditional approaches to computing reliably with unreliable elements, and discuss some of the emerging opportunities.
Bio:
 
Krishna V. Palem is the Ken and Audrey Kennedy Professor at Rice University with appointments in Computer Science, in Electrical and Computer Engineering and in Statistics, and a scholar in the Baker Institute for Public Policy. He was a Moore Distinguished Faculty Fellow at Caltech in 2006-2007, and a Schonbrunn Fellow at the Hebrew University of Jerusalem in 1999, where he was recognized for excellence in teaching. In 2002, he pioneered a novel technology entitled Probabilistic CMOS (PCMOS) and laid the foundations of inexact computing.  PCMOS and its potential applications were respectively recognized as one of the ten technologies ‘likely to change the way we live’ by MIT’s Technology Review in 2008, and as one of the seven ’emerging world changing technologies’ by IEEE as part of its 125th anniversary celebrations in 2009.  In 2012, Forbes (India) ranked him second on the list of eighteen scientists who are “some of the finest minds of Indian origin.” He is a Fellow of the IEEE, the ACM and AAAS, and the recipient of the IEEE Computer Society’s 2008 W. Wallace McDowell Award. He was named a Guggenheim fellow in 2015.

Autonomous Car is the New Driver for Resilient Computing and Design-for-Test

Abstract:
Autonomous or self-driving car initiative is creating a new center stage for resilient computing and design-for-test. This is very apparent from reading the ISO26262 specification, which is about the functional safety for automotive equipment applicable throughout the lifecycle of all automotive electronic and electrical safety-related systems. By way of a brief review of the ISO26262, this talk pays tribute to all of the important and significant ideas that have come through the past 40+ years of research in fault-tolerant computing and design-for-test. One of the key use case for self-driving car is machine learning. Reliability models that explore the dynamic trade-offs between resiliency and performance requirements for machine learning are examined. The talk concludes with a perspective on the most important focus areas for automotive functional safety.
 
Bio:
Nirmal R. Saxena is currently a distinguished engineer at NVIDIA and is responsible for HPC and automotive resilient computing. From 2011 through 2015, Nirmal was associated with Inphi Corp as CTO for Storage & Computing and with Samsung Electronics as Sr. Director working on fault-tolerant DRAM memory and data center storage array architectures. During 2006 through 2011, Nirmal held roles as a Principal Architect, Chief Server Hardware Architect & VP at NVIDIA.  From 1991 through 2009, he was also associated with Stanford University’s Center for Reliable Computing and EE Department as Associate Director and Consulting Professor respectively. During his association with Stanford University, he taught courses in Logic Design, Computer Architecture, Fault-Tolerant Computing, supervised six PhD students and was co-investigator with Professor Edward J. McCluskey on DARPA’s ROAR (Reliability Obtained through Adaptive Reconfiguration) project.  Nirmal was the Executive VP, CTO, and COO at Alliance Semiconductor, Santa Clara. Prior to Alliance, Nirmal was VP of Architecture at Chip Engines. Nirmal has served  in senior technical and management positions at Tiara Networks, Silicon Graphics,  HaL Computers, and Hewlett Packard.
Nirmal received his BE ECE degree (1982) from Osmania University, India; MSEE degree (1984) from the University of Iowa; and Ph.D. EE degree (1991) from Stanford University. He is a Fellow of IEEE (2002) and was cited for his contributions to reliable computing.
 

Quantum error correction and quantum algorithmic discovery

Abstract:
Quantum computers can solve problems in a variety of fields, including number theory, optimization, chemistry, physics, and materials science. Many research groups around the world are working on the challenge of building a quantum computer. The information processing and communication capabilities of such a device would be tremendously different from classical computers. Differences range from speedups for algorithmic problems to the prospect of unconditionally-secure cryptography. Concepts of quantum information and computing have even changed the way researchers think about physics and computers.
I will give an overview of the basic principles of quantum computing, then quickly move on to results on quantum noise models, quantum algorithms and quantum programming languages obtained recently by the QuArC team at Microsoft Research.
 
Bio:
Martin Roetteler received a Ph.D. in computer science from the University of Karlsruhe, Germany, in 2001. Subsequently, from 2003 to 2004 he held a post-doc position at the Institute for Quantum Computing at U Waterloo, from 2005 onward he was a Research Staff Member at NEC Laboratories America, and from 2007 to 2013 he was the leader of NEC’s Quantum IT group in Princeton.  In 2013, Martin joined Microsoft Research in Redmond as a Senior Researcher.  He worked on projects funded by ARO, NSA, the European Union, and the German DFG. He was the main PI of the IARPA QCS project TORQUE, a joint effort between Raytheon/BBN Technologies, NEC Labs America, U Waterloo, and U Melbourne. He published more than 90 refereed journal and conference papers and is co-author of one book on quantum information.  Martin’s research focuses on quantum algorithms, quantum programming languages, and quantum error-correction.