SELSE 2023 technical program

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Thursday March 23, 2023
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Welcome session

Welcome message from the chairsMarcello Traiola, Mario Barbareschi, Sarah Azimi, Angeliki Kritikakou


Keynote 1

Moderator: Sarah Azimi, Politecnico di Torino, Italy
Title: Argotec HAWK Platform: Challenges of Operating Micro-Satellites in Deep-SpaceEmilio Fazzoletto, Head of Electronics Unit, Argotec, Italy

Abstract: Operating a micro-satellite-class platform has always come with many challenges: the small form factor and limited budget most of the times imply leveraging a careful-COTS approach, serious tailoring of applicable space standards commonly used to guarantee mission assurance, and none or little margin for redundancy. In addition, employing such platforms for the unmanned/remote exploration of deep-space increase the challenges: severe limitations of telecommunication opportunities, radiation-related treats and higher cost-per-kg of mass are all factors that further constrain mission and spacecraft design. In this context, Argotec developed a portfolio of avionics products targeting this market niche, producing On-Board Computers (OBCs) and Power Conversion and Distribution Units (PCDUs) which, for the first time, bring high-reliability and radiation-robustness in CubeSat-compatible form factors. These technologies, at the heart of Argotec HAWK Platform, enabled the execution of the first entirely Italian deep-space missions, LICIACube and ArgoMoon. This presentation aims at introducing these missions, Argotec solutions and to discuss some of the reliability strategies successfully employed to guarantee mission assurance.

Author's bio: Emilio Fazzoletto is an Electronic Engineer working in the aerospace industry. He obtained a Master’s Degree in Electronic Systems Engineering at Polytechnic of Turin in 2016, moving to KTH, Stockholm, to work on his Master’s Thesis as exchange student. During his years at university, he joined Squadra Corse Polito, a Formula SAE team, for two seasons. In 2016 he joined Argotec, an expanding Italian aerospace company, developing innovative avionics subsystems for robotic space exploration with micro-satellites. In the context NASA ARTEMIS I and NASA DART missions, he contributed to ArgoMoon and LICIACube missions, designing and operating the first Italian spacecrafts in deep-space. He is now leading Argotec Electronics Units.


Session 1: "Radiation Hardness Assurance: Innovative Approaches"

Moderator: Paolo Rech, University of Trento, Italy
  • Confidence Intervals for Radiation Effects in Microprocessors in Accelerated Neutron Testing
    Charles J. Corley, Heather M. Quinn and Earl E. Swartzlander Jr
  • Programmable SEL Test Monitoring System for Radiation Hardness Assurance
    Daniele Rizzieri, Sarah Azimi, Luca Sterpone, Thomas Borel, Viyas Gupta and Margherita Cardi
  • Toward Understanding Linux Kernel-reported Errors in Radiation Testing
    Charles J. Corley, Heather M. Quinn and Earl E. Swartzlander J




Session 2: "Resilience and Fault Tolerance Computing"

Moderator: Mario Barbareschi, University of Naples, Italy
  • Evaluation of neutron-induced errors on a RISC-V-based SoC
    Fernando Santos, Angeliki Kritikakou and Olivier Sentieys
  • Design with low complexity fine-grained Dual Core Lock-Step (DCLS) RISC-V processors
    Pegdwende Romaric Nikiema, Angeliki Kritikakou, Marcello Traiola and Olivier Sentieys
  • INTERPLAY: An Intelligent Model for Predicting Performance Degradation due to Multi-cache Way-disabling
    Panagiota Nikolaou, Yiannakis Sazeides and Maria Michael
Friday March 24, 2023
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Keynote 2

Moderator: Angeliki Kritikakou, University of Rennes/ Inria, France
Title: Silent Data Corruption Revisited: From Soft Error Resiliency to Silicon Lifecycle ManagementMehdi Tahoori, Professor at Karlsruhe Institute of Technology, Germany

Abstract: As the minimum feature size continues to shrink, a host of vulnerabilities influence the resiliency of VLSI circuits. From the perspective of technology downscaling, the nanoscale effects become harder to model and mitigate at the technology and device levels. The system complexity and added functionalities in existing heterogenous systems further exacerbate the problem. This means VLSI systems become more vulnerable to process and workload-dependent runtime variations as well as various device and interconnect aging effects. On the other side the efficiency of traditional manufacturing testing methods to identify nanoscale failure mechanisms is evading. The combined effect is an increased number of field failures which are referred to as Silent Data Corruption (SDC), fundamentally different from radiation-induced soft errors in the past decades. In this talk I will discuss the progress in modeling and mitigating the combined effects of various sources of manufacturing and runtime variabilities, non-idealities, defects and failures. I will also provide an outlook for Silicon Lifecycle Management to deal with the SDC challenges at nanoscale.

Author's bio: Mehdi B. Tahoori is Professor and the Chair of Dependable Nano-Computing at Karlsruhe Institute of Technology (KIT), Germany. He received the B.S. degree in computer engineering from Sharif University of Technology, Tehran, Iran, in 2000, and the M.S. and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA, in 2002 and 2003, respectively. He is currently the deputy editor-in-chief of IEEE Design and Test Magazine. He was the editor-in-chief of Elsevier Microelectronic Reliability journal. He was the program chair of IEEE VLSI Test Symposium in (VTS) in 2021 and 2018, and General Chair of IEEE European Test Symposium (ETS) in 2019. Prof. Tahoori was a recipient of the US National Science Foundation Early Faculty Development (CAREER) Award in 2008 and European Research Council (ERC) Advanced Grant in 2022. He has received a number of best paper nominations and awards at various conferences and journals. He is currently the chair of IEEE European Test Technologies Technical Council (eTTTC). He is a fellow of the IEEE.


Session 1: "Resilient Deep Learning Accelerators: Design and Evaluation"

Moderator: Marcello Traiola, Inria, France
  • Towards Reliability Assessment of Systolic Arrays against Stuck-at Faults
    Udit Agarwal, Abraham Chan, Ali Asgari and Karthik Pattabiraman
  • Resilience analysis of a Deep Learning hardware accelerator based on systolic arrays
    Salvatore Pappalardo, Annachiara Ruospo, Ian O'Connor, Ernesto Sanchez, Alberto Bosio and Bastien Deveautour
  • Exploiting Machine Learning Potential to Improve DNNs Reliability with Zero-Overhead
    Niccolò Cavagnero, Fernando Fernandes dos Santos, Tatiana Tommasi, Marco Ciccone, Giuseppe Averta and Paolo Rech




Session 2: "Efficient Design and Verification of Circuits"

Moderator: Annachiara Ruospo, Politecnico di Torino, Italy
  • On the automatic generation of workload-aware approximate arithmetic circuits
    Mario Barbareschi, Salvatore Barone, Alberto Bosio, Bastien Deveautour, Ian O'Connor, Ali Piri and Marcello Traiola
  • Fast and accurate estimation of correctness rate in combinatorial circuits based on clustering
    Esther Goudet, Jean-Marc Daveau, Philippe Roche and Lirida Naviner


Closing session

Closing remarks from the chairsMarcello Traiola, Mario Barbareschi, Sarah Azimi, Angeliki Kritikakou

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